1. Field of the Invention
The present invention generally relates to multiplexing synchronous digital data streams, such as video streams. In particular, the present invention relates to the multiplexing of multiple digital data streams while minimizing redundant hardware.
2. Description of the Related Art
In the design of digital camera based systems such as machine vision systems or image acquisition systems, a frequent design task involves accepting data from multiple cameras. The standard methodology for accomplishing this task involves the use of multiple image acquisition devices or frame grabbers. The selection between the images obtained from each camera is typically handled following the acquisition of the images. In other words, each camera has a corresponding image acquisition device. This redundancy in hardware may be quite expensive.
Two prior art approaches to this problem are described as follows.
FIG. 1: FIFO Decoupling System
FIG. 1 illustrates one prior art approach to the above problem, in which a video data stream 104 from each camera is fed into a corresponding FIFO (First In, First Out buffer) 102, then transmitted from the FIFO 102 to a video stream multiplexer (MUX) 110 which selects the video stream to be viewed. Because the video stream data are synchronous, each stream has a corresponding clock signal 106 with a characteristic frequency. Each FIFO 102 receives the input video data at the frequency of the corresponding clock 106, referred to as that FIFO""s write frequency. An output clock signal is selected from one of the camera clocks and is used to synchronize reads from each of the FIFOs. Although this approach works for a selected FIFO which happens to correspond to the clock signal used as the output clock signal, the use of the output clock signal to synchronize reads from one of the other FIFOs may be problematic. For example, if the other FIFO""s write frequency differs from the output clock signal frequency, then FIFO underflow or overflow may occur, as the data will be read faster or slower than the data are written to the FIFO, i.e., the data flow out of the FIFO will be greater or less than the data flow into the FIFO.
FIG. 2: Multiplexed Clock System
FIG. 2 illustrates a second prior art approach to the redundancy problem mentioned above. As FIG. 2 shows, video stream data 104 from each camera is fed to a video stream multiplexer (MUX) 110 which selects the desired video stream and transmits the video stream data to the user. As above, each synchronous video data stream has a corresponding clock signal 106 which is used to synchronize that data stream. Each of the clock signals from the cameras is fed into a clock multiplexer 112 which selects the clock signal corresponding to the selected video stream and transmits the clock signal 106 to the user. However, routing the clock signal 106 through the clock multiplexer 112 may introduce phase errors or delays which can cause violations of the strict synchrony required to utilize the video stream data. If the delay and the clock frequency are both known ahead of time, it is possible to construct a working design around a system in which the clock multiplexer phase shift is not equal to any multiple of the clock period plus or minus some margin for set-up and hold times of the signals. However, if the clock frequency is not known ahead of time, this condition cannot be met and this solution is not workable.
Therefore an improved system and method are desired for multiplexing synchronous digital video streams.
The present invention provides various embodiments of a system and method for multiplexing synchronous parallel digital data streams of different clock frequencies into a single data stream while preserving each data stream""s timing integrity. Embodiments of the present invention may be used in various applications, such as machine vision systems, image acquisition systems, data acquisition systems, etc.
A plurality of digital data inputs and corresponding clock inputs may be coupled to corresponding FIFOs (First In First Out buffers), which may be further coupled to a data multiplexer (MUX). The data MUX may also be coupled to a data acquisition device, which in one embodiment may be further coupled to a computer. Each clock input may also be coupled to a clock MUX which is further coupled to each FIFO and the data MUX. Finally, a transition state machine may be coupled to the clock MUX, the data MUX, and the FIFOs. In one embodiment, the transition state machine may also be coupled to a computer.
In one embodiment, each digital data input may be operable to receive a synchronous digital data stream from a digital source, such as a digital video camera, while the corresponding clock input concurrently receives the corresponding clock signal. It should be noted that each clock signal may have a different frequency and/or phase.
Each of the plurality of FIFOs may transmit its digital data stream to the data stream multiplexer which may select one of the data streams and transmit the selected data stream to a data acquisition device, such as a frame grabber. Each clock input may transmit its clock signal to the clock MUX which may select one of the MUXed clock signals and transmit the selected clock signal to the data MUX, the FIFOs, and the transition state machine. In one embodiment, a clock multiplexer (or a plurality of clock multiplexers) may be used to receive clock signals from the plurality of clock inputs and to select a single clock signal for transmittal to other components of the system.
In one embodiment, the selected clock signal may be transmitted to at least one FIFO corresponding to at least one data stream. In one embodiment, each FIFO may send a data signal to the data MUX on every selected, or MUXed, clock signal pulse. In one embodiment, the selected clock signal may be sent to the data MUX, as well as to the data acquisition device (frame grabber).
The selected clock signal corresponds to the selected data stream, and so the data from the selected data stream is synchronized with its respective clock signal. The fact that the FIFOs which are not selected may also transmit their data according to the selected clock signal (rather than each FIFO""s corresponding clock signal) is not an issue, because the data from the un-selected FIFOs are not used.
The use of FIFOs to decouple the stream output of each camera from the stream input of the data multiplexer combined with the use of the clock multiplexer to select the appropriate clock signal for the selected stream solves the above-mentioned problems of the prior art systems. More specifically, regarding the FIFO underflow/overflow problem of the prior art system described with reference to FIG. 1, by multiplexing the clock signals, selecting the clock signal which corresponds to the selected data stream, and using the selected clock signal to synchronize the output from the selected data stream""s FIFO, the data flow rate out of the selected FIFO will match the data flow rate into the FIFO, thus preventing the underflow/overflow problem. Regarding the phase error problem associated with the prior art system described with reference to FIG. 2, the phase error introduced by the clock multiplexer may be made irrelevant by decoupling the stream output of each camera from the stream input of the data multiplexer through the use of the FIFOs, thus allowing the use of the (possibly phase-shifted) selected clock signal to synchronize the output of the selected stream data from the selected FIFO. The synchronized output data stream may then be selected by the data multiplexer and output along with the selected clock signal. In other words, the FIFO functions as a xe2x80x9cholding tankxe2x80x9d for the selected data stream, and allows the selected data stream to be re-synchronized by the selected clock signal, thus removing the phase shift as an issue.
In one embodiment, each FIFO may also be coupled to a corresponding FIFO control state machine. Each FIFO control state machine may prevent intra-frame transitions to or from its respective FIFO. For example, in the case of a video multiplexing system, the data from each stream may comprise a series of video frames. It may be desirable to prevent transitions between streams (cameras) which give rise to the transmittal of incomplete frames. These transitions may be avoided by restricting transitions to or from a stream to occur between frames, i.e., during a vertical blanking period, or vertical retrace, which may be indicated by an end of frame (EOF) signal. Thus, if a transition is to be made from stream A to stream B, the FIFO control state machine may prevent the transition from FIFO A until the EOF signal for stream A is detected. Then, the FIFO control state machine may prevent reception of stream B data by FIFO B until the EOF signal for stream B is detected. In one embodiment, each FIFO control state machine may flush its corresponding FIFO each time there is a transition from the corresponding stream. In another embodiment, each FIFO control state machine may flush its corresponding FIFO each time there is a transition to the corresponding stream in preparation for reception of new data.
In one embodiment, the transition state machine may be coupled to the data MUX to control the selection of a particular data stream from the MUXed data streams. Similarly, the transition state machine may be coupled to the clock MUX to control the selection of a particular clock signal from the MUXed clock signals. In one embodiment, the transition state machine may receive a selection signal from an external source, such as computer or other external source, and transmit the selection signal to the data MUX and the clock MUX, as well as to the FIFOs.
In one embodiment, the transition state machine may be operable to receive a transition mode signal from the computer or other external source, indicating that intra-frame transitions between streams are to be prevented. The transition mode signal may be transmitted by the transition state machine to the FIFO control state machines to activate this functionality.
In one embodiment, the system may comprise a machine vision or video system where inputs from multiple cameras may be monitored at a central location. The transition state machine may receive periodic selection signals from an automatic scheduler to enable the system to cycle through the cameras on a periodic basis.
In one embodiment, the data MUX may send the selected data stream to the data acquisition device, or frame grabber, where the data may be stored and/or analyzed. Similarly, the clock MUX may transmit the selected clock signal to the data acquisition device to maintain synchrony of the output data stream. In one embodiment, the data acquisition device may be comprised on a circuit card in the computer. In another embodiment, the data acquisition device may be an external device coupled between the computer and the data MUX. In one embodiment, the video stream multiplexing system may be comprised on a circuit board, such as a computer expansion card. In another embodiment, the video stream multiplexing system may be comprised in a chassis, wherein the chassis may further include a power supply which is operable to supply power to the system at the appropriate voltages.